Referring to FIG. 1, a circuit 10 is shown illustrating a conventional deserializer circuit. The circuit 10 generally comprises a full rate phase-locked loop (PLL) 12, a framer circuit 14 and a deserializer block 16. The deserializer block 16 comprises a high speed shifter 18, a parallel load 20 and a state machine 22. The circuit 10 has high power consumption due to (i) the high speed shifter 18, (ii) the parallel load 20 and (iii) the bit rate operation of the state machine 22 and the framer 14.
Referring to FIG. 2, a circuit 10' illustrates another conventional deserializer circuit. The circuit 10' further comprises a barrel shifter 24 and a register 26. The circuit 10' has a higher operating speed than the circuit 10 due to the implementation of the complex framing function at the parallel word rate (as opposed to bit rate), but has higher latency and still has high power consumption due to (i) the high speed shifter 18', (ii) the parallel load 20' and (iii) the bit rate operation of the state machine 22'. FIG. 3 illustrates the high speed shifter 18 (or 18') comprising a number of flip-flops 30a-30n. Each of the flip-flops 30a-30n is timed by the signal PD_CLK.
The circuit 10 and the circuit 10' both require a high speed shifter 18 (and 18') and high speed parallel load 20 (and 20'), which are difficult to implement at high speeds (e.g., at 1 GHz or higher).